The present invention relates to fin field-effect transistors (finFETs), and more specifically, to densely spaced fins for semiconductor finFETs.
Field-effect transistors (FETs) generate an electric field, by a gate structure, to control the conductivity of a channel between source and drain structures in a semiconductor substrate. The source and drain structures may be formed by doping the semiconductor substrate, a channel region may extend between the source and the drain on the semiconductor substrate and the gate may be formed on the semiconductor substrate between the source and drain regions.
The size of FETs has been reduced through the use of fin-based FETs (finFETs), in which the channels of the FET are fin-shaped. Fins of a finFET use a vertical channel structure to increase the surface area of the channel exposed to the gate. As a result, the gate has a greater influence on the channel, because the gate is formed to cover multiple sides of the channel.
The continued miniaturization of electronics has required finFETs to be made continually smaller. However, the size of the fins and the spaces, or pitch, between fins is limited by the lithographic or other etching techniques used to form the fins. One technique currently used to form fins of finFET semiconductor devices is sidewall image transfer (SIT). In SIT, a sidewall spacer is formed on a sacrificial structure, such as a mandrel, which is defined in the present specification as a narrow band of material. The sacrificial material is removed, and the sidewall spacers are then used to etch fins in a silicon-based substrate. In conventional SIT processes, the width of the mandrels and the spaces between the mandrels define the pitch of the fins of the semiconductor device.